Up to the present, memory system designs have combined a variety of memory devices such as semiconductor memory devices (e.g., dynamic RAM, static RAM, flash memory), magnetic discs, and the like. Because of this, it is very difficult to support all of the memory spaces of certain electronic devices, such as personal computers, by using only one sort of memory device.
In the field of semiconductor memories in particular, the development of devices to meet high density, high-speed read/write operations, meet desired access times, achieve low power consumption, etc. have long been required, but there are inevitable limits, as shown by conventional memory devices.
In order to solve the problems stated above, a ferroelectric memory that retains data even when powered off has been created through the use of a ferroelectric material such as a lead zirconate titanate (PZT) exhibiting hysterisis characteristics. Several examples of such ferroelectric memory techniques have been disclosed in the IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1171.about.1175, October 1988, which is entitled "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell."
As is well known in this art, a ferroelectric material has spontaneous polarization characteristics. Directions of the spontaneous polarization are controlled in accordance with directions of an applied electric field. Typical ferroelectric materials, such as an ABO.sub.3 type of PbZrO.sub.3 molecule may be given as an example. In this example, a metal atom, i.e., zirconium (Zr) which is positioned at the center of the PbZrO.sub.3 molecule has two stable state points in accordance with the two possible directions of an applied electric field. Given this zirconium displacement, the zirconium is located in the range of the stable state points. As a result, the ferroelectric material exhibits hysterisis characteristics in an electric field, depending upon the degree of polarization.
A ferroelectric random access memory ("FRAM") is one such semiconductor memory device that uses the hysterisis characteristics of a ferroelectric material. FRAMs achieve nonvolatile storage characteristics by corresponding their degree of polarization to binary data. They are thus capable of performing read/write operations by using a very fast inversing speed of polarization.
Read and write operation of an FRAM can be carried out by polarization reversion, and therefore an operation speed of an FRAM is determined by the time of polarization reversion. The speed of polarization reversion of the ferroelectric capacitor is determined by a capacitor area, a thickness of ferroelectric thin film, an applied voltage, etc., and the unit of the speed of polarization reversion is normally in the range of microseconds (.mu.s). This means that the FRAM can be operated faster than electrically erasable and programmable read only memories (EEPROMs) or flash memories.
FIG. 1 is a graph showing a hysterisis I-V switching loop of a ferroelectric capacitor. In this graph, the abscissa indicates a potential difference between both electrodes of the ferroelectric capacitor, i.e., a voltage between both ends of the capacitor. The ordinate of this graph shows the amount of charge induced to a surface of ferroelectric material in accordance with spontaneous polarization, i.e., the degree of polarization (.mu.C/cm.sup.2).
As shown in FIG. 1, if no electric field is applied to the ferroelectric material that has a zero voltage applied to it, polarization is not mostly caused in domains of polarization. When a voltage is increased in a positive direction of the graph, the degree of polarization is increased from zero up to a point "A" inside the positive charge polarization domain. At the point "A," all of the domains are polarized in one direction and the degree of polarization is maximized. In this case, the degree of polarization, i.e., the amount of charge contained in the ferroelectric material may be indicated as Q.sub.s and the applied voltage as the operation voltage V.sub.cc. After this, even though the voltage is lowered again to zero voltage, the degree of polarization is not reduced to zero, but remains at a point "B." The charge amount of the ferroelectric material, i.e., a remaining degree of polarization obtained by remaining polarization may be depicted as Q.sub.r.
Next, if a voltage is decreased in a negative direction of the graph, the degree of polarization is changed from the point "B" to a point "C" inside the negative charge polarization domain. At the point "C," all of the domains of the ferroelectric material are polarized in a reversed direction with respect to the polarization direction at the point "A." The degree of polarization is then indicated as -Q.sub.s, and the applied voltage as the operation voltage -V.sub.cc. After this, even though the voltage is again brought to zero voltage, the degree of polarization does not go to zero, but remains at a point "D." The remaining degree of polarization may be depicted as -Q.sub.r. If the voltage is increased once more in the positive direction, the degree of polarization is changed from the point "D" to the point "A."
As mentioned immediately above, if a voltage used to cause an electric field is applied once to a ferroelectric capacitor whose ferroelectric material is inserted between two electrodes, the polarization direction according to the spontaneous polarization can be continuously maintained, even though the electrodes are later set to a floating state. Because of this spontaneous polarization, surface charges of the ferroelectric material are not spontaneously dissipated due to leakage. Thus, if the voltage is not applied such that the degree of polarization is at a zero state, the polarization direction continues to be maintained.
As well-known in this art, FRAMs are divided into two classes. One class is called a destructive read-out type ("DRO-type") where data stored in a memory cell is destroyed (or lost) during a read mode of operation. The other class is called a non-destructive read-out type ("NDRO-type") where data stored in a memory cell is not destroyed (or lost) during the read mode of operation.
In the DRO-type FRAM, a unit memory cell consists of one switching transistor and one ferroelectric capacitor (1T/1C) or of two switching transistors and two ferroelectric capacitors (2T/2C), as disclosed in U.S. Pat. No. 4,873,664 ("the '664 patent.) This allows the FRAM to reverse a polarization direction of ferroelectric material sandwiched between a lower electrode and an upper electrode of a ferroelectric capacitor. According to the '664 patent, in the former situation, a memory cell comprises one transistor and one capacitor per one bit and one dummy memory cell, i.e. the reference cell, is provided in the memory cell. In the latter situation, a memory cell comprises two transistors and two capacitors per one bit and a dummy memory cell is not provided in the memory cell. A pair of complementary data is stored in a pair of ferroelectric capacitors.
The DRO-type FRAM operates in a manner similar to that of a dynamic random access memory device except that a refresh operation is not required. But, since data stored in the DRO-type FRAM is read by reversing a polarization direction of a ferroelectric capacitor, it suffers a disadvantage that a rewrite operation (or a writeback operation) must be performed after the read operation to return the ferroelectric capacitor to its proper polarization.
Such methods and devices in which data stored in a memory cell is not destroyed (or lost) during the read mode of operation have been investigated. The NDRO-type FRAM proposed as one such device is disclosed in U.S. Pat. No. 5,753,949 under the title of "FERROELECTRIC MEMORY." The basic structure and operation for an NDRO-type FRAM cell are described in detail in U.S. Pat. No. 5,753,949.
Other NDRO-type FRAMs are disclosed in U.S. Pat. No. 5,345,414 ("the '414 patent") under the title of "SEMICONDUCTOR MEMORY DEVICE HAVING FERROELECTRIC FILM" and in U.S. Pat. No. 5,519,812 ("the '812 patent") under the title of "FERROELECTRIC ADAPTIVE-LEARNING TYPE PRODUCT-SUM OPERATION ELEMENT AND CIRCUIT USING SUCH ELEMENT."
The NDRO-type FRAM device disclosed in the '414 patent uses plural memory cells, each of which includes three transistors, i.e., a writing and erasing transistor, a storing transistor, and a reading transistor. However, since one memory cell is made up of three transistors, the device is unsuited to a high integrity. The NDRO-type FRAM device disclosed in the '812 patent is used as a resistor element of a neuron circuit, but not as a memory element. Given its structure, a writing operation is possible, but a reading operation is impossible.
Furthermore, in a case of manufacturing a memory cell according to the aforementioned methods ('414 and '812 patents), a ferroelectric lattice structure, i.e., a perovskite structure, can be destroyed by a critical chemical reaction or a mutual diffusion between a ferroelectric material, for example, PZT or SBT, and Si (or SiO.sub.2). Therefore, it is another limitation of the aforementioned devices ('414 and '812 patents) that due to a shortness of Pt (lead) in the ferroelectric material, the ferroelectric characteristics may decline.